1. Field of the Invention
The present invention relates to a nonvolatile memory cell that is capable of being electrically written, read and erased, depending on carriers captured by or released from carrier traps formed in a gate insulation film of the memory cell. It also relates to a method of manufacturing such a nonvolatile memory cell.
2. Description of the Prior Art
A known nonvolatile memory device capable of being electrically written, read and erased is an EEPROM.
FIGS. 1a and 1b show a memory cell comprising an EEPROM transistor, having a floating gate. To erase the contents of the memory cell in FIG. 1a, a bias voltage of about, for example, 20 V is applied to a control gate 4 and a bias voltage of about 0 V to a drain region 2 formed on a semiconductor substrate 1, thereby injecting electrons from the drain region 2 into a floating gate 3.
To write the memory cell in FIG. 1b, a bias voltage of about 0 V is applied to the control gate 4 and a bias voltage of about 20 V to the drain region 2, thereby releasing electrons from the floating gate 3 toward the drain region 2.
FIG. 2 shows a memory device comprising a matrixed array of memory cells each including only the above-mentioned transistor.
To write a cell 1 in FIG. 2, a bias voltage of about 0 V is applied to a word line WL1 and a bias voltage of about 20 V to a bit line BL1, thereby establishing a write state of the cell 1.
Due to the bias voltage of about 20 V on the bit line BL1, a cell 3 will be written if a bias voltage of about 0 V is applied to a word line WL2. To avoid this, a bias voltage of about 20 V is applied to the word line WL2. Also, due to the bias voltage of about 0 V on the word line WL1, a cell 2 will be written if a bias voltage of about 20 V is applied to a bit line BL2. To avoid this, a bias voltage of about 0 V is applied to the bit line BL2.
With the word line WL1 being provided with 0 V, word line WL2 with 20 V, bit line BL1 with 20 V and bit line BL2 with 0 V, a cell 4 receives the bias voltage of about 0 V through its drain region and the bias voltage of about 20 V through its control gate, as shown in FIG. 1a. As a result, the cell 4 will be erased to lose information stored therein.
In this way, if each memory cell includes only the transistor of FIG. 1, the memory cells may interact with one another. It is then impossible to select only one of the memory cells to write or erase the one.
To prevent such interactions of memory cells, "Proc. of the 4th on Solid State Devices, Tokyo, 1972" (p. 158) by Iizuka et al. discloses a structure of FIG. 3. According to this, each memory cell comprises a transistor 5 with a floating gate, and a transfer transistor 6. The transistors 5 and 6 are connected in series between a bit line and a ground. By controlling the transfer transistor 6, it is possible to select only one memory cell to write or erase the one.
The structure of FIG. 3, however, needs two transistors for each memory cell.
As explained above, the electrically writable and erasable nonvolatile memory cells each have a single transistor with a floating gate interacting with one another, so that it is impossible to select and write or erase each of the cells.
On the other hand, the arrangement of transfer transistors requires two elements for each memory cell, thereby increasing the area of each cell, to hinder high integration.
In addition, the nonvolatile memory cell having the floating gate requires complicated manufacturing processes compared with a normal MOSFET, due to the floating gate. This increases manufacturing costs.